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*7$ 6hfrqgdu\ &dfkh &rqwuroohu iru 5 )lqdo 5hylvlrq 3ohdvh frqwdfw *dolohr 7hfkqrorj\ iru srvvleoh xsgdwhv ehiruh ilqdol]lqj d ghvljq )($785(6 idt r4600/4700 3 x 16501 tag sram cache data sram external agent (system controller) GT-64012 qs3383 release* extreq* validin* wrrdy* sysad syscmd tag secondary cache address tagop[1:0] vimux tvalidin* gvalidin* grdrdy* gextreq* grelease* scadv*, scads* scdoe*, scdwr* valid sctreset* sctwr* hit scale* scoe* gvalidout* qs3383 validout* syscmd[6] gsvalidout* syscmd[8:3] gwrrdy* 64-bit mips processor zzzjdolohr7frp vxssruw#jdolohr7frp 7ho )d[ ? 6hfrqgdu\ fdfkh frqwuroohu iru wkh elw 0,36 5 plfursurfhvvruv ? /dujh fdfkh vl]h vxssruw - 256kbyte - 512kbyte ? fixed line size - 4 double-words (32 bytes) ? write-through policy ? direct mapping ? physical address and tag ? zero wait-states for cache hit ? supports industry standard synchronous burst srams - 32kx18 - 64kx18 - 32kx36 ? moderate data sram speed required - 12ns for 50mhz ? supports de-facto standard cache tags - 8kx8 tag (idt71b74) - 16kx15 tag (idt71215) ? read burst latency of 3-1-1-1 ? supports all write patterns (dddd or slower) ? supports the r4700s special write modes - pipeline - re-issue ? transparent architecture - design with no logic changes into existing systems ? easy evaluation via galileo-2 cpu module - fits into existing cpu sockets with no board changes to r4600/r4700 system ? compatible with galileo gt-64010 system controller ? minimizes use of external logic components - only 4 standard logic components needed besides memory ? simple way to boost cpu performance - typical improvement range of 20%-100% depend- ing on system architecture and code ? 5 volt operation - easy to incorporate into a 3.3v environment ? :runv zlwk *7$ dqg *7 6\vwhp &rqwuroohuv ? slq 3/&& sdfndjh
*7$ 6hfrqgdu\ &dfkh &rqwuroohu iru 5 29(59,(: the GT-64012 is a secondary cache controller for the mips r4600/4650/4700/5000, which can help system perfor- mance increase by anywhere between 20% and 100%, depending on the system architecture and the nature of the software run by it. the GT-64012 is also compatible with the r4400pc and r4000pc. the architecture of the GT-64012 enables the addition of a secondary cache to an existing system without changes to the system asics or controller logic, for a cost-effective increase in system performance. brand new designs can attain further optimizations. the GT-64012 is designed with bicmos technology to ensure support of fast processor speeds, and to reduce the speed requirement of the tag and data srams, thus reducing system cost. the GT-64012 supports up to 50mhz clock speeds in the bus with no wait-states, which means that it supports the r4600/r4700-100mhz in up to divide-by-2 mode, the r4600/r4700-133mhz, and r4600/r4700-150mhz in up to divide-by-3 mode, and the r4700-166mhz and r4700-175mhz in up to divide-by-4 mode. the GT-64012 supports industry standard synchronous srams with a sub-block ordering burst sequence like the one found in intel processors, thus taking advantage of the economies of scale associated with the pc industry. by support- ing synchronous srams, zero wait-state is attained without the need for interleaving, thus reducing component count, board space, and loading, while improving granularity. only 2 or 4 data srams are needed to build a 256kbyte or 512kbyte cache. at the maximum speed of 50mhz, the GT-64012 only requires the 12ns version of these srams, thus keeping system cost at reasonable levels. the GT-64012 is designed to work with de-facto standard cache tags, very fast srams that include the tag comparison logic on-board. this simplifies the design and ensures no wait-state operation. for a 256kbyte cache, a depth of 8k is needed in the cache tag, whereas for a 512kbyte cache a tag depth of 16k is necessary. the required speed for the address-to-match comparison is 10ns, which is not the fastest tag sram speed available. the tag sram requirement can be reduced to a single chip in the case of the idt71215 16kx15 device if a 512kb cache is used, or two idt71b74 8kx8 devices if a 256kb cache is used. 7kh *7 rshudwhv dv d gluhfw pdsshg zulwhwkurxjk fdfkh zlwk d il[hg olqh vl]h ri e\whv ,w vxssruwv qr zdlw vwdwh rshudwlrq dqg d exuvw uhdg klw sdwwhuq ri )xuwkhupruh lw vxssruwv wkh vshfldo zulwh prghv ri wkh 5 lqfoxglqj slsholqh dqg uhlvvxh ,w vxssruwv wkh '''' zulwh sdwwhuq dv zhoo dv dq\ rwkhu vorzhu sdwwhuqv 7kh plvv |shqdow\ ri wkh vhfrqgdu\ fdfkh lv forfn f\fohv iru zulwh wudqvdfwlrqv forfn f\foh iru qrqfdfkhdeoh uhdg wudqvdf wlrqv dqg forfn f\fohv iru fdfkhdeoh uhdg wudqvdfwlrqv the GT-64012 is housed in a low-cost surface mounted 44-pin plcc package. 5()(5(1&( '(6,*1 a system can be easily retrofitted in one of two ways. first, the r4700 cpu can be replaced by a cpu module that contains all the secondary cache components. an example of this is the galileo-2 module, which is available for evalu- ation, and the reference design of which is available for free (please request your copy). secondly, a motherboard can be easily redesigned to incorporate the cache subsystem knowing that no changes are necessary to the existing con- troller logic or asics. in either case, all that is needed is to adjust the software or firmware to recognize the presence of the secondary cache. brand new designs can use the schematics of the galileo-2 module as a reference, to facilitate the design process. new designs can reduce the miss penalty to 0 clock cycles for writes and non-cacheable read transactions, and 1 clock cycle for cacheable reads. this can be achieved by connecting the system controller to the cpus validout* sig- nal and the tag srams hit signal. the galileo-2 module consists of a small pc board that is plugged into an existing r4600 or r4700 179-pga socket, replacing the cpu. the cpu is then plugged into a similar 179-pga socket on the galileo-2 module. the module con- tains the GT-64012 secondary cache controller, a 16kx15 tag sram, four 32kx18 or 64kx18 burst srams, and 4 standard logic components. a block diagram of it appears on the cover. '(6,*1,1* $ 1(: 6<67(0 :,7+ 7+( *7 when a new system asic is being designed and the GT-64012 is used, it is possible to improve system perfor- mance during reads.
6hfrqgdu\ &dfkh &rqwuroohu iru 5 the GT-64012 distinguishes between two types of reads: uncacheable (partial reads) and cacheable (block reads). all partial reads (syscmd[7:5] = 0 and syscmd[3] = 1), are forwarded to the system a cycle later than the issue cycle on the cpu bus. as both the sysad and syscmd buses are point-to-point connections between the cpu and the sys- tem, a newly designed system asic may monitor syscmd, validout*, tagop0, and tagop1 to detect a partial read request. when a partial read is detected, with both tagop0 and tagop1 inactive, the system asic may start process- ing the transaction immediately, knowing that a cycle later it should ignore the gvalidout* generated by the GT-64012. one cycle is therefore saved. block reads are checked by the GT-64012 for hit or miss in the tag sram. the lookup is done one cycle after valid- out* is asserted. no action is taken by the GT-64012 until the cpu bus is released (read issue cycle). one cycle after the cpu bus is released the GT-64012 asserts gvalidout* if the lookup turned to be a miss so as to forward the request to the system. a newly designed system asic may monitor the hit signal during the look-up phase to determine in advance if the request will be forwarded to the system or not. if a hit occurs, no action should be taken as data will be returned from the secondary cache. if a miss occurs, the system asic may start processing the request ignoring the gvalidout* which will be generated by the GT-64012 at least a cycle later. care should be taken to keep track over cpu bus status (released or not) before sysad and syscmd get driven by the system; i.e., grelease* should be monitored for asser- tion before syscmd and sysad are truly released. in systems where rdrdy* is constantly asserted, grelease* will be asserted two cycles after the issue cycle. in most systems, rdrdy* is constantly asserted or even tied to ground so the same cycle in which validout* is firstly asserted is also the issue cycle. such systems may simplify the decision making involved in this process. the gt-64010 system controller from galileo takes advantage of this methodology to provide a system designer with maximum performance when also using the GT-64012 secondary cache controller. '(7(50,1$7,21 2) 6(&21'$5< &$&+( 35(6(1&( 9,$ 62)7:$5( it is possible to utilize a simple software mechanism to determine if a GT-64012 is present in the system or not. the sequence of transactions to be made is as follows (all are addressed to the same cache line): 1. cacheable read (block); 2. first level cache invalidate (cache operation) or two first level cache line replacements; 3. uncacheable write; 4. cacheable read. if the returned data from step 4 is updated by the written data in step 3, the GT-64012 is not present in the system, and vice versa. &203$7,%,/,7< :,7+ 9 6<67(06 it is easy to interface the 5v GT-64012 to a 3.3v cpu subsystem. the block diagram that appears on the cover needs to be augmented only by one component. the existing components are already 3.3v-compatible. the burst synchronous srams are available in 3.3v vcc versions with 5v-tolerant inputs and thus can interface directly to the GT-64012. tag srams like the idt71215 can have their i/os working from a 5v or 3.3v source, while the supplied vcc is 5v, and thus can work in a mixed voltage environment. the fct163501 3.3v bidirectional latches can be used instead of the 5v version, since their inputs are still 5v tolerant. the quickswitches used to gate the validout and validin signals provide an effective mechanism to interface between 5v and 3.3v. consequently, the only extra component needed is another quickswitch to interface the GT-64012 outputs extreq* and grelease*, plus the i/os syscmd[8:3], to the 3.3v subsystem. the qs3384 when supplied with 4.3v works as an effective 5v to 3.3v converter with zero delay. this is illustrated in the figure below.
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6hfrqgdu\ &dfkh &rqwuroohu iru 5 3,1,1)250$7,21 /rjlf 6\pero reset* syscmd[8:3] tagop1 validout* tvalidin* release* tclk scale hit valid sctreset* sctwr* scdwr* scdoe* scadv* scads* scoe* GT-64012 cpu interface initialization secondary cache interface system interface gvalidin* hitdly tagop0 extreq* vimux te s t grelease* grdrdy* gwrrdy* gextreq* gvalidout*
*7$ 6hfrqgdu\ &dfkh &rqwuroohu iru 5 3lq$vvljqphqw7deoh pin name sync to type drive description initialization reset* --------- i reset: initializes the internal state of the GT-64012. hitdly tclk i hit delay: configuration bit for the r4600 versions. 0: zero wait states during hits (r4600 version 2.0 or higher) 1: one wait state during hits (r4600 version 1.7) te s t i test: tri-states all outputs. 0: normal functioning 1: tri-state outputs cpu bus release* tclk i release: in response to the assertion of extreq* or a cpu read request, the cpu asserts release*, signaling to the GT-64012 that the system interface is available tagop1 tclk i tag ram operations 1: a high during a partial read address space causes a tag sram flush. this input typi- cally connects to a high order address bit (e.g. sysad[31]). tagop0 tclk i tag ram operations 0: a high during a partial read address space invalidates a specific tag sram entry. this input typically connects to a high order address bit (e.g. sysad[30]). the entry to be invalidated is defined by the address of the transaction. note that tagop1 and tagop0 should not be high simultaneously during a par- tial read address phase. syscmd[8:3] tclk i/o 16ma (32ma) 1 system command: upper 6 bits of command and data identifier. tvalidin* tclk o 8ma (32ma) valid in: asserted when the GT-64012 drives valid data onto the sysad bus and valid data identifier onto the syscmd bus during block read hit or tag sram opera- tions. validout* tclk i valid out: used by the GT-64012 as an indication that the cpu is driving a valid address or data on the sysad bus and a valid command or data identifier on the syscmd bus. extreq* tclk o 2ma (32ma) external request: the GT-64012 asserts this signal to request use of the system interface. tclk --------- i transmit clock: system clock input. vimux tclk o 12ma (32ma) validin multiplexing: controls the no-delay external mul- tiplexer (qs3383q) selecting the source of cpu validin* from the tvalidin* signal supplied by the GT-64012 or the gvalidin* signal supplied by the system controller. system bus gextreq* tclk i system external request: provided by the system con- troller, it controls the extreq* output of the GT-64012. only external write and external null requests are sup- ported.
6hfrqgdu\ &dfkh &rqwuroohu iru 5 $oo gulyh vwuhqjwkv lq sduhqwkhvhv hj p$ uhihu wr wkh rul jlqdo *7 dv r ssrvhg wr wkh qhz *7$ grdrdy* tclk i system read ready: when asserted by the system con- troller, it indicates that the system can accept a cpu read request. grelease* tclk o 20ma (32ma) system release: in response to the assertion of gex- treq* or a cpu partial read or block read miss, the gt- 64012 asserts grelease*, signaling to the system con- troller that the system interface is available. gvalidin* tclk i system valid in: asserted when the system controller drives valid address or data onto the sysad bus and valid data identifier onto the syscmd bus, during cpu reads or external requests. gvalidout* (1) o 20ma (32ma) system valid out: indicates to the system controller that the cpu or the GT-64012 is driving a valid address or data onto the sysad bus and a valid command or data identifier onto the syscmd bus. gwrrdy* i system write ready: indicates that the system control- ler can accept a cpu write request. scoe* tclk o 12ma (32ma) secondary cache output enable: provides output enable control of the external bidirectional latches (fct16501). active during partial reads and block read misses to drive address and command onto the system controller. cache interface scale (2) o 8ma (32ma) secondary cache address latch enable: provides latch enable control to the external bidirectional latches (fct16501). it is used to latch the address and command at issue. hit tclk i hit: indicates a valid match in the tag ram. valid tclk o 2ma (32ma) valid: validates tag entry during block write and block read miss (line fill). invalidates tag entry during tag inval- idate operation. sctreset* tclk o 2ma (32ma) secondary cache tag reset: a reset signal to the tag ram, asserted during a tag flush operation. sctwr* tclk o 2ma (32ma) secondary cache tag write: controls writes to the tag ram. scdwr* tclk o 12ma (32ma) secondary cache data write: enables data writes to the cache data srams. activated during block write and block read miss (line fill). scdoe* tclk o 12ma (32ma) secondary cache data output enable: enables data output from the cache data srams. activated during block read hit. scadv* tclk o 12ma (32ma) secondary cache advance: synchronously advances the cache data sram internal burst address. scads* (3) o 16ma (32ma) secondary cache address strobe: synchronously latches the burst start address in the cache data srams. pin name sync to type drive description
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6hfrqgdu\ &dfkh &rqwuroohu iru 5 )81&7,21$/'(6&5,37,21 ,qlwldol]dwlrq ,qwhuidfh reset* initializes the internal state of the GT-64012. it does not initialize the tag ram entries. the configuration pin (hitdly) is sampled during reset to determine whether to have zero or one wait-state in read hit cycles. this is designed to accommodate rev. 1.7 versions of the r4600. the pin is sampled during the last four tclk cycles in which reset* is asserted. when hitdly is sampled high, there is one wait-state during read hits to support rev. 1.7 r4600s. when hitdly is sampled low, there are no wait-states on read hits. reset* and tclk must be connected to the cpu reset input and tclk output. &38 ,qwhuidfh ? block read request in a block read request and a hit in the secondary cache, the data will be supplied from the cache and the GT-64012 will not forward the request to the system interface (gvalidout* is not asserted). in a miss in the secondary cache, the GT-64012 forwards the request to the system by asserting gvalidout* and grelease* two tclks after receiving the request from the cpu. the address and the command, which are no longer available from the cpu, are driven onto the sysad and syscmd buses from the bi-directional latches (16501), by means of the GT-64012 asserting scoe*. when the data is returned from the system to the cpu, the GT-64012 writes the line into the secondary cache (performs a line fill). ? uncached read requests in an uncached read request the GT-64012 forwards the request to the system one tclk cycle after receiving the request. when the system returns the data, the GT-64012 forwards it to the cpu without writing it to the secondary cache. ? block write request in a block write request the GT-64012 forwards the request to the system by asserting gvalidout* in the same tclk the request is issued by the cpu (validout* is asserted). concurrently the GT-64012 writes the line to the cache and updates the tag and valid bit in the tag ram. the GT-64012 supports all write patterns of the r4600 (dddd, dxdxdxdx, etc.). ? uncached write request in an uncached write request, the GT-64012 forwards the request to the system in the same tclk that the request is issued from the cpu. the cache is not updated. ? flush the cpu can flush the secondary cache by executing an uncached read request with tagop0 low and tagop1 high. the GT-64012 will not forward this cycle to the system bus. it will reset the entire tag ram and return undefined data to the cpu three tclks from validout*. this means that the entire tag ram is cleared (flushed). ? cache entry invalidate the cpu can invalidate an entry in the secondary cache tag ram by performing an uncached read with tagop0 high and tagop1 low. the entry pointed by the address on sysad[5:17/18] will be invalidated (17 or 18 as a function of the size of the data srams used). note that both flush and cache entry invalidate operations return undefined data. the GT-64012 always drives syscmd[4] to check parity. thus if the system is parity-protected, the cpus parity checking should be turned off when executing cache operations. ? external requests the GT-64012 supports external write requests and external null requests. it does not support external read requests. all external requests are forwarded to the cpu without GT-64012 intervention.
*7$ 6hfrqgdu\ &dfkh &rqwuroohu iru 5 ? read ready the cpus rdrdy* pin is connected to vss (always active). the external agent drives the GT-64012s grdrdy* signal. ? write ready the external agent drives wrrdy* to both the GT-64012 and the cpu. 6\vwhp ,qwhuidfh the system interface transfers cpu cycles to the system bus. it transfers read responses and external requests from the system bus to the cpu via the 16501s. &dfkh ,qwhuidfh the GT-64012 supports industry standard synchronous burst srams. examples of this are the idt 71420 32kx18 and the motorola 67b618 64kx18. synchronous burst sram number of tag entries number of srams cache size 32k x 18 8k 4 256kb 32k x 36 8k 2 256kb 64k x 18 16k 4 512kb
6hfrqgdu\ &dfkh &rqwuroohu iru 5 3,12877$%/(6 slq 3/&& 6ruwhg $oskdehwlfdoo\ vss pins - 11, 18, 19, 22, 33, 44 vdd pins - 1, 10, 12, 23, 34 slq 3/&& 6ruwhg %\ 3lq 3rvlwlrq pin # signal name pin # signal name pin # signal name pin # signal name 40 extreq* 39 release* 35 sctwr* 9 tclk 25 gextreq* 15 reset* 3 syscmd[3] 16 test 27 grdrdy* 28 scads* 4 syscmd[4] 32 valid 20 grelease* 29 scadv* 5 syscmd[5] 42 tvalidin* 24 gvalidin* 37 scale 6 syscmd[6] 41 validout* 21 gvalidout* 31 scdoe* 7 syscmd[7] 14 vimux 26 gwrrdy* 30 scdwr* 8 syscmd[8] 38 hit 13 scoe* 2 tagop0 17 hitdly 36 sctreset* 43 tagop1 pin # signal name pin # signal name pin # signal name pin # signal name 1 vdd 12 vdd 23 vdd 34 vdd 2 tagop0 13 scoe* 24 gvalidin* 35 sctwr* 3 syscmd[3] 14 vimux 25 gextreq* 36 sctreset* 4 syscmd[4] 15 reset* 26 gwrrdy* 37 scale 5 syscmd[5] 16 test 27 grdrdy* 38 hit 6 syscmd[6] 17 hitdly 28 scads* 39 release* 7 syscmd[7] 18 vss 29 scadv* 40 extreq* 8 syscmd[8] 19 vss 30 scdwr* 41 validout* 9 tclk 20 grelease* 31 scdoe* 42 tvalidin* 10 vdd 21 gvalidout* 32 valid 43 tagop1 11 vss 22 vss 33 vss 44 vss
*7$ 6hfrqgdu\ &dfkh &rqwuroohu iru 5 $&7,0,1*&+$5$&7(5,67,&6 (tc= 0-70 0 c; vdd= +5v, +/- 5%, 50 pf except where noted) notes: 1. reads only 2. writes only 3. deassertion 4. assertion 5. 20pf load for GT-64012a (samsung) 6. 20pf load for GT-64012 (temic) *7$ *7 symbol signals description min max min max unit t1 tclk pulse width high 8 8 ns t2 tclk pulse width low 8 8 ns t3 tclk clock period 20 20 ns t3a tclk rise time 2 2 ns t3b tclk fall time 2 2 ns t4a syscmd[8:3] system driven setup to tclk 3.5 3.5 ns t4b syscmd[8:3] cpu driven setup to tclk 8 8 ns t5 validout*, release*, tagop1, tagop0 setup to tclk 8 8 ns t6 hit setup to tclk 7 7 ns t7 gwrrdy*, gvalidin*, gextreq* setup to tclk 4 4 ns t8 grdrdy* setup to tclk 4 4 ns t9 syscmd[8:3], validout*, release*, tagop1, tagop0, gextreq*, gwrrdy*, grdrdy*, gvalidin*, hit hold from tclk 1 1 ns t10 grelease* gvalidout* 1 delay from tclk delay from tclk 2 2 8 8 2 2 8.5 8 ns t11 scale delay from tclk falling edge 3838ns t12 sctreset* 5 , sctwr* 5 , valid 5 , scdwr*, scadv* delay from tclk 2 10 2 10 ns t13 extreq* 5 , syscmd[8:6] delay from tclk 2 12 2 12 ns t14 vimux 5,6 delay from tclk rising edge 2929ns w *9dolg2xw 'hod\iurp6\v&pg>@ qv w 6&$g6 'hod\iurp9dolg2xw qv w 6&$g6 'hod\iurp6\v&pg>@ qv w scoe* rising delay from tclk 2 2 ns w scoe* falling delay from tclk 2 2 ns w scdoe* rising delay from tclk qv w scdoe* falling delay from tclk qv w validin* 5,6 delay from tclk qv
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*7$ 6hfrqgdu\ &dfkh &rqwuroohu iru 5 '&(/(&75,&$/63(&,),&$7,216 7& & 9'' 9 symbol parameter min. max. unit conditions vih input high voltage 2.0 vdd+0.5 v vil input low voltage -0.5 0.8 v voh output high voltage 2.4 v vol output low voltage 0.4 v iin input leakage current -10 10 ua vin = vdd or gnd ioz 3-state output leakage current -10 10 ua vout = vdd or gnd icc operating current 100 ma vdd = 5v, ta=25c cinclk clk input capacitance 7.5 pf cin input capacitance 5 pf cout output capacitance 5 pf
6hfrqgdu\ &dfkh &rqwuroohu iru 5 6) packaging 6.1 44-pin plcc ( all dimensions given in millimeters ) 18 19 20 21 22 23 24 25 26 27 28 16.55 0.11 17.525 0.125 1.27 29 30 31 32 33 34 35 36 37 38 39 17 16 15 14 13 12 11 10 98 7 16.55 0.11 17.525 0.125 6 5 4 3 2 1 44 43 42 41 40 1.245 0.175 0.737 0.77 0.254 0.051 seating plane 0.433 0.10 12.70 0.433 0.10 15.494 0.51 4.38 0.19 2.67 0.25 0.762 0.25
*7$ 6hfrqgdu\ &dfkh &rqwuroohu iru 5 5(9,6,21+,6725< revision history for rev. 2 vs. rev. 1: note: these are documentation revisions, the GT-64012s chip has not changed, but some ac parameters have been tightened. 1. ac timing characteristics have been changed, reclassified, or split as follows: a) the minimum values of tclks pulse width high and pulse width low (t1 and t2) have changed from 7 to 8ns. b) the minimum value of scale (t11) has changed from 2 to 3ns. c) the maximum values for scads* (t16 and t17) have been tightened from 8 to 6ns. d) scoe* has been removed from t12, and has been given the symbols t20 and t21 for rising and falling values, respectively. the maximum value for scoe* rising (t20) has been tightened from 10 to 8.5ns. the maximum value for scoe* falling (t21) has been tightened from 10 to 6.5ns. e) scdoe* has been removed from t12, and has been given the symbols t22 and t23 for rising and falling values, respectively. the maximum value for scdoe* rising (t22) has been tightened from 10 to 9ns. the maximum value for scdoe* falling (t23) has been tightened from 10 to 8ns. f) validin* has been removed from t13 and has been given the symbol t24. the maximum value for validin* has been tightened from 12 to 9.5ns. 2. clarification has been added on the test load conditions of the ac timing characteristics 3. a package profile drawing has been added. revision history for rev. 3 (october 1997) vs. rev. 2: 1. GT-64012a device information added. 2. t10 for grelease* increased from 8ns to 8.5ns for GT-64012 only. 3. t16 for scads* increased from 6ns to 7ns for GT-64012 only.

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